This invention relates to electronics, in general, and to integrated circuits and methods of operation, in particular.
Phase Lock Loops (PLLs) are used in a wide variety of electronic applications. In general, a PLL has a phase frequency detector, also known as a phase detector, a charge pump, a loop filter, a Voltage-Controlled Oscillator (VCO), and a clock divider. Low output impedances of current sources in the charge pump cause several problems including phase offset, phase noise, and jitter due to the resulting mismatch in up and down currents into the loop filter. Cascoding techniques can be used to increase output impedance, but the resulting high drain-to-source saturation voltages in output transistors of the charge pump also cause several problems including decreased output dynamic range. Similarly a Metal-Oxide-Semiconductor (MOS) output device in the current source can be made with a long channel length to increase output impedance, but the long channel length adds to the capacitance of the circuit. The higher capacitance reduces the speed of the circuit, but higher speeds are required in applications such as a PLL charge pump.
Accordingly, a need exists for an integrated circuit comprised of a fast current source with a high output impedance and low output drain-to-source saturation voltages.
In accordance with the principles of the invention, a first embodiment of an integrated circuit comprises a first three-terminal device; a second three-terminal device; a third three-terminal device, a first terminal of the third three-terminal device coupled to first terminals of the first and second three-terminal devices, a second terminal of the third three-terminal device coupled to second terminals of the first and second three-terminal devices and to a third terminal of the third three-terminal device; a fourth three-terminal device; an amplifier comprising two inputs and an output, a first one of the two inputs coupled to a first terminal of the fourth three-terminal device and to a third terminal of the second three-terminal device, a second one of the two inputs coupled to a third terminal of the first three-terminal device, the output coupled to a second terminal of the fourth three-terminal device; a first current source comprising an output; a second current source comprising an output coupled to the output of the first current source and to a third terminal of the fourth three-terminal device; and a fifth three-terminal device, a first terminal of the fifth three-terminal device coupled to the output of the first current source, a third terminal of the fifth three-terminal device coupled to the third terminal of the third three-terminal device.
Further, in accordance with the principles of the invention, a second embodiment of the integrated circuit comprises a first n-channel MOSFET comprising first source, gate, and drain electrodes; a second n-channel MOSFET comprising second source, gate, and drain electrodes; a third n-channel MOSFET comprising third source, gate, and drain electrodes, the first, second, and third source electrodes coupled to each other, the first, second, and third gate electrodes coupled to each other and to the third drain electrode; a fourth n-channel MOSFET comprising fourth source, gate, and drain electrodes, the fourth source electrode coupled to the second drain electrode; an amplifier comprising negative and positive inputs and an output, the negative input coupled to the fourth source electrode and to the second drain electrode, the positive input coupled to the first drain electrode, the output coupled to the fourth gate electrode; a first current source comprising an output coupled to the fourth drain electrode; a second current source comprising an output coupled to the fourth drain electrode and to the output of the first current source; and a first p-channel MOSFET comprising fifth source, gate, and drain electrodes, the fifth source electrode coupled to the outputs of the first and second current sources and to the fourth drain electrode, the fifth drain electrode coupled to the third drain electrode and to the first, second, and third gate electrodes.
Still further, in accordance with the principles of the invention, an embodiment of a method of operating an integrated circuit comprises providing a first current; generating a second current to replicate the first current; generating a reference current; subtracting the second current from the reference current to create a net current; and adjusting a value of the net current.